Dmitry Petrov is a Senior Architect with 11+ years of focused experience designing high-speed mixed-signal SerDes systems and clocking architectures, currently leading advanced projects at Synopsys in Ottawa. He has hands-on expertise in analog and digital PLLs up to 30 GHz, SAR-ADC based receiver frontends, and delivered first-silicon success across 56–224 Gb/s SerDes designs published in ISSCC. Dmitry combines deep circuit-level skills (VCOs, DFEs, phase interpolators) with large-scale mixed-signal verification, calibration algorithm development, and practical lab validation. He has led cross-functional teams from architecture through tapeout at Huawei and Intel, bridging process nodes from 7 nm to 180 nm. Beyond silicon, he contributes to open-source ML docs in scikit-learn, showing an unexpected knack for communicating complex concepts to a broader developer audience. Colleagues rely on him for pragmatic system trade-offs that translate cutting-edge analog techniques into production-ready SoCs.
11 years of coding experience
30 years of employment as a software developer
Arizona State University
Master of Science (MS) RF Engineering, Master of Science (MS) RF Engineering at Peter the Great St.Petersburg Polytechnic University
Contributions:10 commits, 5 PRs, 18 comments in 17 days
Contributions summary:Dmitry's contributions primarily involve enhancing the documentation of machine learning models within the scikit-learn library. They added examples to the docstrings of various models including RandomForestClassifier, RandomForestRegressor, PassiveAggressiveClassifier, PassiveAggressiveRegressor, LinearSVC, LinearSVR, MinMaxScaler, StandardScaler, ElasticNet, and ElasticNetCV. These additions help users understand how to implement and use the models correctly through practical code examples.
Contributions:23 pushes, 1 branch in 1 year 4 months
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