Dmitry Smekhov
FPGA Design Engineer at Inline Group
Serbia
Summary
👤
Senior🎓
Top SchoolDmitry Smekhov is an FPGA Design Engineer with over nine years of professional experience and a multi-decade background in FPGA and DSP systems engineering. He has designed and led FPGA projects across Xilinx families from Spartan to Versal/UltraScale, integrating high-speed ADC/DAC, DDR3/DDR4, PCIe (including x16 Gen3), and multi-gigabit serial links. As a part-time Xilinx instructor for SDAccel, Vitis OpenCL, PCIe, Versal ACAP and Vitis AI, he blends hands-on implementation with teaching cutting-edge workflows for hardware-accelerated compute. Dmitry has held leadership roles building DSP labs and researching 10G/100G Ethernet and Zynq-based solutions, and now operates as an independent FPGA consultant. Based in Serbia, he brings deep protocol- and silicon-level expertise and a knack for turning complex analog/front-end requirements into robust digital designs.
9 years of coding experience
16 years of employment as a software developer
engineer-electronic, engineer-electronic at Moscow State Institute of Radio Engineering, Electronics and Automation (Technical University)
Github Skills (2)
digital-design8
gpu1
Programming languages (3)
Github contributions (5)
dsmv/sdaccel
Jul 2017 - Oct 2017
Contributions:1 release, 36 commits, 2 PRs in 2 months
dsmv/basics-graphics-music-fork
Aug 2023 - Nov 2024
FPGA exercise for beginners
Contributions:13 pushes in 1 year 2 months
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