Dominik Salvet is a Staff Hardware Design Engineer with 8 years of hands-on experience designing high-performance RISC-V processors and microarchitectural features. He has driven branch predictor and BTB innovations, led area- and latency-optimized FPU design, and delivered synthesis-based PPA gains (up to -32% area, -40% dynamic power) across embedded cores. Comfortable with SystemVerilog, HLS-like CodAL, and open-source CPU work, he has extended superscalar and SIMD-capable pipelines and contributed practical B-extension and packed-SIMD implementations. Based in Brno, he blends low-level RTL craftsmanship with customer-facing technical leadership and a knack for squeezing PPA improvements out of real silicon-feasible designs. An uncommon strength is translating high-level ISA and parallelism concepts into compact, low-power microarchitectures used in production-class cores.
8 years of coding experience
2 years of employment as a software developer
Master's degree, Embedded Systems, Master's degree, Embedded Systems at Brno University of Technology
Bachelor's degree, Programmable Technical Structures, Bachelor's degree, Programmable Technical Structures at Masaryk University Brno
High School Diploma, Electronic Computer Systems, High School Diploma, Electronic Computer Systems at SŠIEŘ Rožnov pod Radhoštěm
Contributions:10 releases, 771 commits, 9 PRs in 2 years 7 months
simple-gitpackage-managerpackage-basedcli
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