Donggyu Kim
Student at ucb-bar
Summary
🤩
RockstarDonggyu Kim is a compiler-focused backend developer and graduate student at UC Berkeley with 12 years of engineering experience contributing to high-profile open-source hardware tooling. He has made substantive compiler and backend improvements to Chisel, FIRRTL, and Rocket Chip—fixing width inference, memory/readwrite port handling, and refactoring backend implementations to improve compatibility and performance. Donggyu’s work spans bug fixes, optional inference features, and test automation, demonstrating both low-level RTL expertise and rigorous QA practices. He’s comfortable navigating compiler internals and emulator/backend tradeoffs, including replacing emulators with Verilator in chisel3 workflows. Colleagues can expect a pragmatic engineer who balances maintenance of legacy behavior with thoughtful architectural changes. His profile reflects deep, less obvious domain knowledge in hardware compiler toolchains rather than general-purpose software.
12 years of coding experience
Github Skills (26)
verilog10
back-end-development10
testing10
generator10
firrtl10
intermediate-code10
scala10
compiler-design10
compiler-compiler10
intermediate-language10
chisel10
rt10
hdl10
compiler10
chip810
Programming languages (6)
Github contributions (5)
chipsalliance/firrtl
Jul 2016 - Jul 2019
Flexible Intermediate Representation for RTL
Role in this project:
Back-end Developer & Compiler Engineer
Back-end Developer & Compiler EngineerContributions:118 commits, 90 PRs, 255 pushes in 3 years
Contributions summary:Donggyu primarily worked on improving the Flexible Intermediate Representation for RTL (FIRRTL) compiler, a core component of the repository. Their commits focused on fixing memory port enable signals and improving the handling of readwrite ports for backward compatibility. The user also removed a constant propagation step to address errors related to SIntLiterals and made the infer-rw part optional.
representationtransformationintermediate-representationrtlcompiler
ucb-bar/chisel-tutorial
Sep 2014 - Aug 2016
chisel tutorial exercises and answers
Role in this project:QA Engineer / Test Automation Engineer
QA Engineer / Test Automation EngineerContributions:12 commits, 2 PRs, 6 pushes in 1 year 11 months
Contributions summary:Donggyu primarily contributed to the testing of the `chisel-tutorial` repository. Their commits demonstrate the addition and modification of test cases for various Chisel modules, including `ResetShiftRegister`, `EnableShiftRegister`, and `Risc`. The user implemented tests for different Chisel backends and also fixed bugs related to shift register testing. The user also updated test drivers.
pythonsmttlachiselelectrical-engineering
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