Dustin Deweese is a creator and software engineer with 14 years of experience applying formal logic and mathematics to hardware and software design. Based in Mountain View, he builds practical tools spanning language design, compilers, digital logic, theorem proving, and real-time embedded signal processing. He released a fast, elegant 3D modeling app for iOS (noumenal.app) and contributes to notable open-source projects including Verilog-to-Routing (VTR) for FPGA CAD flows and the Bevy game engine, improving FPGA assembly mapping, geometry libraries, and rendering pipelines. His work blends low-level FPGA and embedded toolchains with high-level graphics and engine development, reflecting a rare cross-domain fluency. A master’s graduate in computer science from Wright State University, he brings both academic rigor and product-focused delivery to complex systems. Colleagues know him for thoughtful, correctness-driven design and practical engineering that surfaces from formal foundations.
14 years of coding experience
Masters, Computer Science, Masters, Computer Science at Wright State University
A refreshingly simple data-driven game engine built in Rust
Role in this project:
Full-stack Developer
Contributions:80 reviews, 18 PRs, 160 comments in 4 years 1 month
Contributions summary:Dustin primarily contributed to the game engine's rendering and graphics capabilities, fixing bugs related to iOS GPU usage and implementing features for rendering flexibility. Their work included modifying the `winit_runner` to prevent crashes on iOS when the app is suspended, supporting different primitive topologies beyond the default triangle list for mesh rendering, and correcting shadow rendering for non-triangle list meshes. They also implemented functionality to render to textures and added support for vertex colors in meshes. Additionally, they refactored code related to global transforms to use Affine3A.
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Contributions:34 reviews, 57 commits, 34 PRs in 1 year 5 months
Contributions summary:Dustin primarily focused on improving the Verilog-to-Routing (VTR) flow by adding new features to the FASM (FPGA Assembly) component, enabling a flexible mapping of parameters. They also addressed typos and improved code formatting and readability within the VPR (Versatile Place and Route) and VTR codebases. Furthermore, they updated and extended the geometry library with additional features.
vtrcadedaplacementsynthesis
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