Eddie Hung
Founder at FPG-eh Research
Vancouver, British Columbia, Canada
Summary
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Rockstar🎓
Top School
Top expert inDigital Hardware Design and Verification
Eddie Hung is an electronic engineer and founder with 11 years of industry and academic experience spanning FPGA research, toolchains, and embedded systems. He earned a PhD focused on using FPGAs for rapid circuit debug and has continued that work by driving open-source FPGA tooling through FPG-eh Research and substantial back-end contributions to widely used projects like Yosys and nextpnr. Previously a technical lead whose product was acquired, he pairs hands-on low-level coding (technology mapping, flip-flop initial-value handling, place-and-route fixes) with research rigor from roles at Imperial College and UBC. Based in Vancouver, he blends practical product delivery and academic depth, often improving toolchain internals and test cases rather than just high-level features.
11 years of coding experience
7 years of employment as a software developer
PhD, Electrical and Computer Engineering, PhD, Electrical and Computer Engineering at The University of British ColumbiaMEng, Electronic and Communications Engineering, MEng, Electronic and Communications Engineering at University of Bristol
Stackoverflow
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Github Skills (11)
fpga10
verilog10
c-language10
cprogramming-language10
computer-engineering9
hdl9
hardware-designs9
pg7
cmake7
algorithms6
algorithm6
Programming languages (5)
Github contributions (5)
YosysHQ/yosys
Apr 2015 - Sep 2021
Yosys Open SYnthesis Suite
Role in this project:
Back-end Developer
Back-end DeveloperContributions:5 reviews, 3335 commits, 470 PRs in 6 years 5 months
Contributions summary:Eddie's contributions primarily involved technology mapping within the Yosys Open SYnthesis Suite, specifically focusing on the ABC9 technology mapping flow. Their work included modifying existing code files and test cases to improve the tool's functionality. The user's contributions also focused on handling initial values for flip-flops within the AIGER backend and the associated optimizations.
synthesispythonsuiteyosys
YosysHQ/nextpnr
Jul 2018 - May 2020
nextpnr portable FPGA place and route tool
Role in this project:Back-end Developer
Back-end DeveloperContributions:420 commits, 41 PRs, 54 pushes in 1 year 10 months
Contributions summary:Eddie contributed to the `nextpnr` project, an FPGA place and route tool. Their commits focused on enhancing the tool's functionality, including code improvements and addressing potential issues with string handling. They also integrated changes from other repositories, which may involve code refactoring, improving code readability and maintainability, and integrating external contributions, or addressing bug fixes or performance improvements. Additionally, the user made various updates to comments to improve code clarity and maintainability.
placenextpnrplace-and-routexilinxhaiku
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