Summary
Eduardo Corpeño is a Silicon Engineering Specialist based in Ottawa with over 25 years of electronics and verification experience and 11 years in silicon-focused roles, currently validating complex SoCs at Accenture using SystemVerilog, UVM and automated RTL rule flows. He pairs deep academic leadership—nearly two decades as Electrical Engineering Lab Director at Universidad Galileo—with hands-on RTL and gate-level debug, static analysis (Lint, CDC, RDC) and CI-driven regression automation. Comfortable writing tooling in Python, C++, Java and shell, he bridges verification, design and architecture teams to improve RTL hygiene and signoff readiness. Eduardo’s background in analog/digital circuit design, hardware prototyping and on-site system commissioning gives him a practical edge when troubleshooting root causes that span silicon to board-level. He holds an MSc in Computer Science from Georgia Tech and a BS in ECE, bringing both rigorous theory and applied engineering to deliver robust, tape-out-ready designs.
11 years of coding experience
Master of Science (MSc), Computer Science, Master of Science (MSc), Computer Science at Georgia Institute of Technology
BS, Electrical and Computer Engineering, BS, Electrical and Computer Engineering at Universidad Francisco Marroquín
French, English, Spanish