Summary
Eduardo Mendes is a Senior Engineer in System Architecture with eight years of hands-on experience designing FPGA and high-speed digital systems for institutions like CERN and industry leaders such as Kandou AI and Axelera AI. He combines academic rigor (PhD-level training) with practical skills in FPGA SerDes, control loops, DSP, and HDL-to-hardware verification, delivering first-time-right solutions for time-synchronization and optical link systems. Comfortable leading international teams across five countries and fluent in English, French and Portuguese, he pairs lab instrumentation expertise with automated Python testbenches and clear scientific communication. Unusually, his work bridges deep hardware design (including 28nm ASIC optimizations and DDR/DMA systems) with algorithmic prototyping in Python/Matlab and published collaborations that include Xilinx engineers and adoption by NIST and APS.
8 years of coding experience
9 years of employment as a software developer
Federal University of Rio Grande do Norte
M. Eng. Electronics and Signal Processing, M. Eng. Electronics and Signal Processing at ENSEEIHT
National Conservatory of Arts and Crafts
Portuguese, French, English, German