Ekaterina Berezina
Senior CPU Design Engineer at Arm
Cambridge, England, United Kingdom
Summary
👤
Senior🎓
Top SchoolEkaterina Berezina is a Staff HW Design Engineer based in Cambridge with over a decade of hands-on experience in CPU IP development, specializing in architecture and microarchitecture definition, RTL design, verification, and PPA optimization for both ASIC and FPGA. She has deep practical experience across Intel, RISC-V and ARM ecosystems, advancing from intern roles at Intel Labs to senior and staff positions at Syntacore and Arm. Ekaterina combines academic rigor—teaching a master’s-level SoC Design course—with production engineering, delivering configurable SystemVerilog CPU cores and leading timing/area/power trade-offs. Known for bridging theory and practice, she often translates classroom concepts into silicon-ready RTL and verification flows.
8 years of coding experience
7 years of employment as a software developer
Bachelor's degree, Computer Science, Bachelor's degree, Computer Science at ITMO University
Russian, English
Github Skills (7)
risc-v10
ip10
verilog10
risc10
mcu7
instruction-set3
sdk3
Programming languages (3)
Github contributions (5)
sc-itmo-edu/scr1
Mar 2020 - Nov 2020
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Contributions:4 PRs, 3 pushes, 3 branches in 8 months
risc-vriscvhigh-qualityriscin-core
eb-sc/scr1
Apr 2019 - Apr 2019
SCR1 is an open-source RISC-V compatible MCU core
Contributions:2 PRs, 1 push, 3 branches in 1 day
risc-vriscvriscmcu
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