Enze Chi
FPGA Engineer at Optiver Asia Pacific
Greater Sydney Area Australia
Summary
👤
Senior🎓
Top SchoolEnze Chi is an experienced FPGA and ASIC engineer with over 15 years in high-performance hardware design and 8 years focused on FPGA work, currently driving low-latency FPGA solutions at Optiver Asia Pacific. He combines deep RTL expertise in Verilog/SystemVerilog/VHDL with practical verification skills using UVM, SVA and Python-driven regressions, and has hands-on experience with Cadence/Synopsys/Mentor flows. His career spans telecommunications and high-speed networking projects at Cisco, Finisar and Blackmagic Design, where he designed and integrated Ethernet/IP blocks, QDR interfaces and complex traffic management logic. Comfortable across Linux and Windows toolchains, he also programs in C++ and automates flows with shell and Python, and is bilingual in Mandarin and English. Notably, he has led both design and verification efforts as project manager on line-card and SPA card programs, demonstrating the rare combination of architect-level design thinking and day-to-day verification/debugging rigor.
8 years of coding experience
17 years of employment as a software developer
UNSW Sydney
English, Chinese
Github Skills (96)
bash-configuration10
bash10
vim10
spacemacs10
bash-completion10
melpa10
atlassian10
emacs-lsp10
emacs-lisp10
emacs10
shell10
wrapper10
shell-extension10
evil-mode10
crowd9
Programming languages (7)
Github contributions (5)
ezchi/yasnippets-verilog
Jun 2019 - Jul 2021
Contributions:23 commits, 14 pushes, 3 branches in 2 years 1 month
ezchi/verilog-mode
Feb 2018 - Feb 2021
Contributions:53 pushes, 5 branches in 3 years 1 month
verilog-modeindentationmastergnuemacs
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