Eric Gouriou
Staff Software Engineer at Google
Sunnyvale, California, United States
Summary
🤩
Rockstar🎓
Top SchoolEric Gouriou is a Staff Software Engineer based in Sunnyvale with a decades-long career spanning roles at Google, Rivos, Apple, HP, and Oracle, blending deep systems engineering with technical leadership. He has strong embedded and back-end expertise, recently contributing significant RISC-V Vector Cryptography (Zvk) instruction support to the widely used Spike ISA simulator—work that touches low-level ISA parsing, new instruction fields, and cryptographic vector primitives. At Rivos he held a principal engineering role and now returns to Google as a staff engineer, demonstrating a pattern of operating at the intersection of hardware-software co-design and production-grade systems. He pairs academic credentials from CentraleSupélec and an MS from UCLA with practical delivery across chip- and platform-scale projects, and often moves between individual contributor and technical lead roles. A less obvious thread in his career is a sustained focus on cryptographic and vector acceleration features that enable secure, high-performance computation in emerging RISC-V ecosystems.
4 years of coding experience
24 years of employment as a software developer
Diplôme d'Ingénieur, Diplôme d'Ingénieur at CentraleSupélecUniversity of California, Los Angeles
Github Skills (6)
risc-v10
c-language10
cprogramming-language10
cryptography10
assembler9
assembly9
Programming languages (4)
Github contributions (5)
riscv-software-src/riscv-isa-sim
Apr 2023 - Jun 2023
Spike, a RISC-V ISA Simulator
Role in this project:
Back-end Developer / Embedded Systems Engineer
Back-end Developer / Embedded Systems EngineerContributions:22 reviews, 2 PRs, 35 comments in 2 months
Contributions summary:Eric primarily focused on implementing and integrating RISC-V Vector Cryptography (Zvk) instructions within the RISC-V ISA simulator. Their work involved parsing extensions, defining new instruction fields (zimm6), and implementing the instructions for Zvbb, Zvbc, Zvkg, Zvkned, Zvknh[ab], Zvksed, and Zvksh extensions. The contributions include the addition of new macros and the implementation of instructions for vector bit manipulation, carryless multiplication, and NIST suite instructions.
risc-visariscvriscv32simulator
rivosinc/riscv-isa-sim
Jan 2023 - Feb 2023
Spike, a RISC-V ISA Simulator
Contributions:11 commits, 41 pushes, 4 branches in 22 days
risc-visariscvsimulatorrisc
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