Eric Schkufza
Senior Principal Engineer at You.com
Berkeley, California, United States
Summary
👤
Senior🎓
Top SchoolEric Schkufza is a Senior Principal Engineer based in Berkeley with 15 years of experience at the intersection of programming languages, compilers, and high-performance computing. He holds a PhD in Computer Science from Stanford and has blended deep research roles (VMware Research, Microsoft Research) with industry impact as a Principal Scientist at Amazon and as an engineering co-founder at Graft. Eric specializes in machine-code optimization for hardware accelerators and is known for working effectively when source code is unavailable, a niche that combines reverse engineering with compiler optimization. His background includes expert code review for IP litigation and practical systems work from Bloomberg to large cloud providers, giving him rare cross-domain fluency. At you.com he now applies this expertise to production-scale engineering challenges, translating cutting-edge research into deployed systems. Colleagues would describe him as a researcher-practitioner who prefers solving low-level, high-impact problems that others call impossible.
15 years of coding experience
11 years of employment as a software developer
BSE Computer Science and Computer Engineering (dual degree), BSE Computer Science and Computer Engineering (dual degree) at The University of Michigan, Ann ArborPhD Computer Science, PhD Computer Science at Stanford University
Github Skills (41)
verilog10
lattice10
assembly10
synthesizer10
stochastic10
vmware10
hardware10
eda10
x8610
vhdl10
midi10
x86-6410
assembler10
fpga10
nasm10
Programming languages (4)
Github contributions (5)
vmware-archive/cascade
Sep 2018 - Feb 2020
A Just-In-Time Compiler for Verilog from VMware Research
Contributions:1073 commits, 175 PRs, 957 pushes in 1 year 5 months
vhdledalatticecompilervmware
eschkufz/cascade
Mar 2020 - Dec 2020
A Just-In-Time Compiler for Verilog from VMware Research
Contributions:64 commits, 38 PRs, 64 pushes in 8 months
compilervmwarejust-in-timeverilog
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