Erqi Deng
Design Verification Intern
Palo Alto, California, United States
Summary
👤
Senior🎓
Top SchoolErqi Deng is a design verification engineer and Ph.D. student with eight years of hands-on experience in hardware and embedded systems, currently interning at Cisco where they apply SystemVerilog/UVM to block-level verification and automation scripting. With a strong academic foundation from University of Washington (BE, 3.99 GPA) and ongoing MS studies in Electrical Engineering at Stanford, Erqi blends RTL verification skills with circuit-level lab experience using oscilloscopes, waveform generators, and simulation tools. They bring seven years of robotics design and programming expertise across Verilog, Python, Java, C, and C++, and have contributed to sensor development projects—such as single-walled carbon nanotube ammonia sensors and dielectric spectroscopy-based ripeness detectors—highlighting an ability to move ideas from prototype to technical reports and proposals. Fluent in Mandarin and English, Erqi also has teaching experience as a TA, demonstrating clear communication and mentorship in addition to deep technical capability.
8 years of coding experience
Bachelor of Engineering - BE, Electrical and Computer Engineering, 3.99/4.0, Bachelor of Engineering - BE, Electrical and Computer Engineering, 3.99/4.0 at University of WashingtonMaster of Science - MS, Electrical Engineering, Master of Science - MS, Electrical Engineering at Stanford University
Github Skills (5)
inverse10
renderer8
utf8
rendering4
rendering-engine3
Programming languages (3)
Github contributions (5)
erqihuang/Spectral-Propagation-Net
Jan 2022 - Dec 2022
Contributions:18 commits, 15 pushes, 2 branches in 10 months
erqihuang/erqihuang.github.io
Apr 2022 - May 2024
Contributions:11 pushes, 2 branches in 2 years 2 months
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