Summary
Ethel M is an experienced SoC and FPGA engineer with 11 years in telecommunications, specialising in PHY design, real-time embedded DSP and signal processing for 5G and NTN. She combines MATLAB algorithm development and validation with hands-on implementation on Xilinx platforms (Zynq, RFSoC, Versal), including RTL, HLS, Petalinux, Vitis and AI Engine work. Her background spans satellite communications system sizing and link-budget analysis at Thales Alenia Space to PHY algorithm design at Octasic and recent senior DSP work at E-Space, giving her both system-level and low-level implementation fluency. Based in Sherbrooke with engineering training from INSA Rennes and a satellite communications credential from Oxford, she brings a rare mix of academic grounding and practical FPGA/SoC delivery. Notably, she moves fluidly between MATLAB simulation and production-targeted programmable architectures, accelerating algorithm-to-hardware cycles.
11 years of coding experience
4 years of employment as a software developer
French Master’s degree in Engineering Electrical and computing engineering, French Master’s degree in Engineering Electrical and computing engineering at INSA Rennes
Baccalauréat Scientifique, Baccalauréat Scientifique at Broceliande's High School
Satellite Communications and Navigation : Technologies Markets and Applications, Satellite Communications and Navigation : Technologies Markets and Applications at Oxford Lifelong Learning, University of Oxford
Semestre d'échange en génie électrique, Semestre d'échange en génie électrique at Université de Sherbrooke
French, English