Eugene Tarassov
Principal Member Of Technical Staff at AMD
Danville, California, United States
Summary
🤩
Rockstar🎓
Top SchoolEugene Tarassov is a Principal Member of Technical Staff at AMD with over three decades of engineering experience focused on semiconductors, embedded software and on-chip debugging. He has led the Eclipse TCF project and driven debugger internals and GUI work across ARM, RISC-V and MicroBlaze platforms, blending deep low-level expertise with open-source stewardship. Previously a principal engineer at Xilinx and technologist at Intel and Wind River, he pairs FPGA hardware design and Vivado block-level contributions with systems software and Linux debugging support. His GitHub work on Vivado RISC-V SoC designs highlights hands-on FPGA integration—Ethernet controller fixes, board porting and memory/reset logic—showing he still codes at the silicon-software boundary. Based in Danville, CA, he combines a Master’s in Physics/Computer Science from Novosibirsk State University with rare institutional memory of embedded tooling evolution.
8 years of coding experience
21 years of employment as a software developer
Master, Physics, Computer Science, Master, Physics, Computer Science at Novosibirsk State University (NSU)
Github Skills (14)
ethernet10
fpga10
embedded10
vivado10
xilinx10
sys10
system8
architecture8
microcontroller8
architectures8
jtag7
risc-v6
c176
c116
Programming languages (4)
Github contributions (5)
eugene-tarassov/vivado-risc-v
Feb 2020 - Jan 2023
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Role in this project:
Embedded Systems Engineer / FPGA Developer
Embedded Systems Engineer / FPGA DeveloperContributions:13 releases, 337 commits, 14 PRs in 2 years 11 months
Contributions summary:Eugene primarily contributes to the Xilinx Vivado block designs for a RISC-V SoC, indicated by modifications to Tcl scripts for design generation, and changes to VHDL/Verilog code of the Ethernet controller. The commits suggest work on low-level hardware aspects, memory configurations, and system resets, indicating the user's focus is on hardware integration and interfacing within the FPGA. Contributions included porting the code to support different boards, implementing fan control and memory addressing logic, and fixing the Ethernet driver.
risc-vvivadoxilinx-vivadoriscvxilinx
Joel-Dandin/vivado-risc-v
Jan 2023 - Feb 2023
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Contributions:7 commits in 22 days
risc-vvivadoxilinx-vivadoxilinxlinux
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