Fabian Schuiki
Senior Compiler Engineer at SiFive
Mountain View, California, United States
Summary
🤩
Rockstar🎓
Top SchoolFabian Schuiki is a Senior Compiler Engineer at SiFive with 14 years of expertise in energy-efficient high-performance computing and a PhD in Computer Hardware Engineering from ETH Zurich. He designs compiler and hardware toolchains—authoring LLHD and the Moore open-source hardware design flow and creating the Bender dependency manager—bridging research-grade ideas with practical developer tooling. His contributions to projects like LLVM/CIRCT and Chisel show deep backend and lowering experience, including FIRRTL-to-LLHD conversion and nuanced width/signedness fixes that improve generator correctness. Fabian pairs hands-on SystemVerilog component development and verification with compiler-level passes, giving him rare full-stack fluency across RTL, IRs, and build ecosystems. Based in Mountain View, he combines academic rigor with production engineering at scale, often tackling subtle edge cases (e.g., zero-width handling and name sanitization) that quietly make hardware toolchains robust.
14 years of coding experience
Exchange Year, Electrical and Electronics Engineering, Exchange Year, Electrical and Electronics Engineering at Imperial College LondonBachelor’s degree, Electrical Engineering and Information Technology, Bachelor’s degree, Electrical Engineering and Information Technology at ETH Zürich
German, English, French
Stackoverflow
1,278reputation
103kreached
33answers
16questions
Github Skills (41)
hardware-designs10
verilog10
c-language10
systemverilog10
firrtl10
mlr10
scala10
compiler-optimization10
fifo10
cprogramming-language10
hardware9
verification9
compiler-design9
code-generation9
formal-verification9
Programming languages (14)
Github contributions (5)
llvm/circt
Oct 2020 - Oct 2022
Circuit IR Compilers and Tools
Role in this project:
Back-end Developer & Compiler Engineer
Back-end Developer & Compiler EngineerContributions:2 releases, 1849 reviews, 315 commits in 2 years
Contributions summary:Fabian focused on implementing a foundational conversion pass for FIRRTL modules to their LLHD entity counterparts, including adding lowering for the `firrtl.connect` operation. They improved code stability and maintainability by addressing issues with name sanitization, enforcing proper use of LLHD types. Further contributions included addressing a regression introduced by a previous commit, and improving handling of zero-width types during width inference. The user also worked on improving the testing infrastructure for code verification and performance.
compilersbazelmlircircuitunikernel
pulp-platform/common_cells
Apr 2018 - Sep 2018
Common SystemVerilog components
Role in this project:Embedded Systems Engineer / Automation Engineer
Embedded Systems Engineer / Automation EngineerContributions:4 reviews, 16 commits, 5 pushes in 5 months
Contributions summary:Fabian primarily contributed to SystemVerilog code, developing and modifying hardware components, including a CDC FIFO, stream register, stream multiplexer, and round-robin arbiter. They also wrote testbenches to verify the functionality of these components, demonstrating a focus on hardware verification. Additionally, the user made changes to improve assertion logic and introduced a new FIFO version with configurable thresholds.
systemverilog
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.