Fang Li
Design Verification Engineer
Beijing, United States
Summary
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Rockstar🎓
Top SchoolFang Li is a Design Verification Engineer with nine years of hands-on experience in mixed-signal and high-speed IO validation, currently contributing to NVIDIA’s verification efforts. He has deep expertise in GPU IO subsystems, NVLINK, PCIe, USB, SerDes, and PLL characterization, built on earlier roles validating Ethernet PHYs and ADC/DACs at Marvell. Fang holds two master’s degrees in electrical engineering with specializations in ASIC and analog/mixed-signal design, bringing both system-level validation insight and circuit-level measurement experience. Based in Beijing with a global career footprint, he blends rigorous test methodology with practical lab characterization skills to close the loop between silicon behavior and system requirements. A pragmatic problem-solver, Fang is known for bridging analog measurement challenges and digital verification flows to accelerate time-to-silicon.
9 years of coding experience
10 years of employment as a software developer
M.S Electrical Engineering, ASIC Design, M.S Electrical Engineering, ASIC Design at Auburn UniversitySan José State UniversityB.S, Electronics and Information Engineering, B.S, Electronics and Information Engineering at Dalian University of TechnologyProgramming languages (1)
Github contributions (5)
CAS-CLab/DGNet
Oct 2021 - Dec 2022
Contributions:2 commits, 1 push, 1 branch in 1 year 1 month
lfr-0531/TensorRT-LLM
Mar 2025 - Apr 2025
TensorRT-LLM provides users with an easy-to-use Python API to define Large Language Models (LLMs) and build TensorRT engines that contain state-of-the-art optimizations to perform inference efficiently on NVIDIA GPUs. TensorRT-LLM also contains components to create Python and C++ runtimes that execute those TensorRT engines.
Contributions:29 pushes, 4 branches in 8 days
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