Farid Anjidani
Senior R&D Engineer at Synopsys Inc
Greater Vancouver Metropolitan Area Canada
Summary
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Senior🎓
Top SchoolFarid Anjidani is a Senior R&D Engineer with 8 years of experience bridging hardware and software, specializing in C/C++, Python, and Verilog for embedded systems and real-time applications. He holds an MS in Computer Hardware Engineering and has driven firmware and algorithmic development—from converting Python test frameworks to performant C implementations to designing lightweight logging and NFC data-transfer solutions. His research background includes efficient CNNs for ultrasound image enhancement and implementation of SSIM-based video quality modules using Catapult HLS and Verilog, reflecting strong hands-on RTL and algorithm integration skills. Based in Greater Vancouver, he combines academic rigor with industry impact at companies like Xtrava Health, NETINT, Ansys, and Synopsys, and is particularly drawn to projects that sit at the intersection of neural networks and resource-constrained hardware.
8 years of coding experience
5 years of employment as a software developer
Master of Science - MS, Computer Hardware Engineering, Master of Science - MS, Computer Hardware Engineering at University of VictoriaElectrical Engineering (Computer Architecture and Digital Systems), Electrical Engineering (Computer Architecture and Digital Systems) at University of TehranNational Organization for Development of Exceptional Talents (Sampad)
English, PersianProgramming languages (1)
Github contributions (5)
faridanjidani/ESPCN-inference-Using-C-
Dec 2021 - Sep 2022
Contributions:2 pushes, 1 branch in 9 months
faridanjidani/red_parrot_code
Dec 2018 - Aug 2019
Contributions:6 pushes in 8 months
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