FarshadĀ
Sr. Staff Engineer at Alpha and Omega Semiconductor
Cupertino, California, United States
Summary
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Seniorš
Top SchoolFarshad is a seasoned verification engineer and technical leader with nine years of hands-on experience in VLSI front-end verification, now serving as Senior Staff Engineer in Cupertino. He has deep expertise in SystemVerilog and UVM across complex protocols (AMBA APB/AHB/AXI, PCIe), mixed-signal and analog verification for sensor SoCs and PMICs, and has led teams and projects from specification to sign-off. At Ulkasemi he progressed through roles from Associate Verification Engineer to Technical Manager, managing cross-functional teams, formal assertion work, coverage-driven verification, and system-level chip simulations in processes from 180nm down to sub-20nm. Known for pairing rigorous testbench engineering with pragmatic project management, he also writes automation scripts (Python, Tcl, Bash) and mentors junior engineers. Outside work he is an avid reader and lifelong learner, a trait that fuels his continual adoption of new verification methods.
9 years of coding experience
9 years of employment as a software developer
SSC Science, SSC Science at Model AcademyH.S.C Science, H.S.C Science at BCIC collegeMaster of Science - MS Information and Communication Technology , Master of Science - MS Information and Communication Technology at Institute of Information and communication Technology (IICT), Bangladesh University of Engineering and Technology (BUET)Bachelor's Degree Electrical Electronics and Communications Engineering, Bachelor's Degree Electrical Electronics and Communications Engineering at Military Institute of Science and Technology (MIST)
English, Bangla
Github Skills (11)
slave9
amba8
render8
markup6
uvm5
specification5
verification5
verilog5
markdown5
testbench4
vip4
Programming languages (1)
Github contributions (5)
courageheart/AMBA_APB_SRAM
Jun 2018 - Jul 2018
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
Contributions:15 commits in 1 month
verilogapbambacomplaintspecification
farshad112/ring_oscilator
Oct 2018 - Oct 2018
Contributions:10 commits, 6 pushes, 1 branch in 1 day
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