Fatemeh Javaheri
ASIC Digital Design, Principal Engineer at Synopsys Inc
Vaughan, Ontario, Canada
Summary
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Senior🎓
Top SchoolFatemeh Javaheri is a Principal ASIC Digital Design Engineer with over 15 years of experience building and verifying FPGA and SoC designs, now driving advanced RTL work at Synopsys after a multi-year tenure at Intel. She combines deep academic rigor (PhD-level research in correct-by-construction circuit synthesis) with hands-on delivery of production features such as Quartus partial reconfiguration, security, and performance modeling. Known for creating high-performance, resource-efficient RTL and for leading formal, assertion-based, and UVM verification efforts, she also architected fast NoC bandwidth modeling and synthesis engine optimizations. Fatemeh has led cross-functional teams, developed large automated test suites and verification infrastructures, and translated complex specs into deployable flows and customer-facing documentation. She brings a rare mix of research-driven tools (e.g., SyntHorus2) and practical engineering impact—specializing in making brittle FPGA flows robust, measurable, and secure. Based in Vaughan, Ontario, she thrives on continuous learning and solving subtle design and verification challenges end-to-end.
8 years of coding experience
11 years of employment as a software developer
Master of Engineering (M.Eng.), Computer Engineering, Master of Engineering (M.Eng.), Computer Engineering at University of TehranKooshesh High SchoolDoctor of Philosophy (PhD), Electrical and Electronics Engineering, Doctor of Philosophy (PhD), Electrical and Electronics Engineering at Institut national polytechnique de Grenoble
English, FrenchProgramming languages (1)
Github contributions (1)
intel/fpga-partial-reconfig
May 2018 - Aug 2018
Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
Contributions:1 release, 32 commits, 9 pushes in 3 months
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