Fatima Saleem
Staff Engineer at 10xEngineers
Lahore, Punjab, Pakistan
Summary
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Rockstar🎓
Top SchoolFatima Saleem is a Staff Engineer specializing in RISC-V core and SoC design with five years of hands-on experience in RTL design, verification, and automation. She has deep expertise in the RISC-V Privileged spec and IOMMU IP, contributed key MMU and extension support to the open-source CVA6 core, and led coverage closure efforts on SiFive cache subsystems. At 10xEngineers she moved from design and verification into chiplet packetizer RTL work, blending system-level protocol understanding (PCIe/CXL) with low-level datapath and vector LSU design. An active OpenHW committer, she pairs rigorous verification practices—install scripts, Verilator updates, and lint fixes—with practical simulation and logging improvements that improve reproducibility and CI robustness. Based in Lahore, Fatima combines academic mechatronics training with a pragmatic drive to advance open-source RISC-V silicon for edge and application-class use cases.
4 years of coding experience
6 years of employment as a software developer
BSc Engineering, Mechatronics & Control Engineering, BSc Engineering, Mechatronics & Control Engineering at University of Engineering and Technology, Lahore
English, Chinese, Urdu
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (21)
systemverilog10
scripting10
risc-v10
cpu10
bash10
verilator10
automation10
script10
systemverilog-hdl10
yaml10
sh10
automations10
shell10
uvm9
cicd9
Programming languages (5)
Github contributions (5)
openhwgroup/cva6
Dec 2021 - Jan 2025
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:8 reviews, 22 PRs, 55 comments in 3 years 1 month
Contributions summary:Fatima primarily worked on modifying and improving the CVA6 core, a RISC-V CPU capable of booting Linux. Their contributions include creating installation scripts and configuration files for running RISC-V architecture tests, replacing and cleaning up linker files, and modifying logging within the CVA6 simulation environment. They also updated the Verilator version and resolved various lint warnings, indicating a focus on code quality and system-level aspects of the processor design.
cpurisc-vasicbootingariane
openhwgroup/core-v-verif
Apr 2022 - Jul 2022
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:DevOps Engineer & Automation Engineer
DevOps Engineer & Automation EngineerContributions:1 review, 14 commits, 1 PR in 2 months
Contributions summary:Fatima's contributions primarily revolve around setting up and maintaining the build and verification environment for the CORE-V family of RISC-V cores. They created and modified install scripts, YAML files, and configuration settings to integrate and run RISC-V architecture tests. Furthermore, the user focused on managing dependencies by updating Verilator versions, modifying linker configurations, and adjusting logging settings to align with the CVA6 model. These commits show a focus on automation and ensuring the proper functioning of the verification flow.
risc-vsystemverilogriscverificationcores
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