Fazia Batool is a Senior Verification Engineer based in Austin with 8 years of experience building and validating complex IP for leading silicon companies, currently at Arm after a high-impact tenure at Intel. She has led verification teams, architected debug and testbench migrations using SystemVerilog/OVM/UVM, and drove volume verification improvements that cut failure buckets and boosted functional coverage using ML-guided analysis. Her work spans PCIe Gen4/Gen5 IP, cache-coherent interconnects, and automation of regression and coverage workflows, earning departmental awards for legacy stimulus reuse and tooling that scaled cross-functional debugging. Fazia blends hands-on RTL and verification coding with mentorship and process improvements, and she’s particularly skilled at turning randomized regression data into actionable failure signatures and resource savings.
8 years of coding experience
St. Mary's Senior Secondary School
Master's degree, Computer Engineering, 3.6/4, Master's degree, Computer Engineering, 3.6/4 at Texas A&M University
Bachelor of Technology - BTech, Electronic and Communications Engineering, 8.73/10, Bachelor of Technology - BTech, Electronic and Communications Engineering, 8.73/10 at Jamia Millia Islamia
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