Florent Rotenberg
Grenoble, Auvergne-Rhône-Alpes, France
Summary
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RockstarFlorent Rotenberg is an embedded systems and digital IC engineering specialist with nine years' experience in architecture, specification, design and verification for ASIC, FPGA and SoC projects. He combines technical project leadership—planning, risk management and reporting—with deep hands-on expertise in SystemVerilog/UVM verification, low-power UPF/CPF flows, and a wide EDA toolset (Cadence, Synopsys, Mentor). His background spans MCU/CPU/DSP cores, memory and communication IP, mixed-signal SoC integration, and FPGA Zynq/UltraScale+ designs, alongside firmware and driver development in C/C++ for ARM Cortex targets. Comfortable with scripting and version control (Python, Bash, Perl, Tcl, Git/SVN), he bridges system-level architecture and practical verification delivery to accelerate time-to-silicon. Notably, he leverages community project platforms like Tuleap, Wrike and GitLab to streamline collaboration and traceability across multi-discipline teams.
9 years of coding experience
English, French
Github Skills (51)
deterministic10
pulp10
systemverilog10
uvm10
cpu10
fixed-point10
risc10
timing9
risc-v9
floating9
parametric8
electrical-engineering8
floating-point8
lattice7
debug7
Programming languages (7)
Github contributions (5)
pulp-platform/timer_unit
Jun 2018 - Sep 2019
Contributions:8 pushes, 2 tags in 1 year 3 months
pulp-platform/apb_gpio
Mar 2017 - Sep 2019
Contributions:7 commits, 5 pushes, 4 tags in 2 years 6 months
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