Florian Zaruba
Principal Engineer - Computing Architecture at OpenHW Group
Zurich, Zurich, Switzerland
Summary
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Rockstar🎓
Top SchoolFlorian Zaruba is a Principal Engineer in Computing Architecture based in Zurich with 11 years of experience designing and delivering high-performance CPU and SoC solutions. He blends deep RTL and system-level expertise—SystemVerilog, cache and memory-hierarchy fixes, AXI interconnects—with hands-on silicon experience, having designed, manufactured and tested multiple 22nm/65nm ASICs and booted Linux on RISC-V cores. At ETH Zurich he led the Occamy many-core chiplet project and now drives computing architecture at Axelera AI while also directing HW & SW task groups at OpenHW Group, bridging open-source cores and industrial adoption. His open-source contributions to projects like the CORE-V CVA6 and PULP AXI IP show a knack for low-level fixes that prevent subtle bugs (e.g., address aliasing and AXI ID remapping), reflecting a rare combination of research rigor and production-grade engineering.
11 years of coding experience
4 years of employment as a software developer
Vienna University of TechnologyDoctor of Science, Integrated Circuit Design, Doctor of Science, Integrated Circuit Design at ETH Zürich
English, Spanish, German
Github Skills (18)
verilog10
systemverilog10
axi410
ip10
cpu-architecture10
digital-logic10
digital-design10
ax10
sys10
rt10
fpga10
embedded10
logic10
hardware9
memory-management9
Programming languages (14)
Github contributions (5)
pulp-platform/common_cells
Mar 2018 - Sep 2021
Common SystemVerilog components
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:16 releases, 20 reviews, 95 commits in 3 years 6 months
Contributions summary:Florian primarily focused on developing and modifying SystemVerilog components, specifically for the `fifo_v3` implementation and related testbenches. Their work involved adding and refining features such as FIFO usage output, as well as addressing issues and improving code quality through linting and test updates. Furthermore the user created various digital components and peripherals, which included clock dividers, counters and arbiters.
systemverilog
openhwgroup/cva6
Aug 2017 - Jan 2022
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:2 releases, 301 reviews, 744 commits in 4 years 6 months
Contributions summary:Florian's commits involve modifying the CVA6 core's low-level functionality. The changes include adapting the memory interface. This work focuses on fixing a potential address aliasing issue within the cache subsystem and implementing a system bus access module. This demonstrates a strong understanding of memory hierarchy and low-level CPU architecture.
cpurisc-vasicbootingariane
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