Francesco Conti
Associate Professor
Bologna, Emilia-Romagna, Italy
Summary
🤩
Rockstar🎓
Top SchoolFrancesco Conti is an Associate Professor at the University of Bologna with 11+ years of experience researching and engineering energy-efficient heterogeneous multicore systems for embedded AI. He blends academic leadership and hands-on RTL and embedded-C design—contributing to well-known open-source PULP projects (CV32E40P, PULPissimo, PULPino) where he implemented CPU tracing, FPGA flows, clocking primitives and build-system fixes. His work spans architecture-to-silicon co-design, low-power brain-inspired accelerators, and practical deployment of deep-learning workloads on constrained SoCs, informed by postdoctoral and visiting stints at ETH Zurich and Stanford. A two-time IEEE best-paper awardee and frequent peer reviewer, he coordinates hardware-acceleration efforts within the PULP Platform and consults industry on neural processing engines. Outside research he pursues photography, politics and mountain hiking, reflecting a practical curiosity that often guides his cross-layer fault-resilience and energy-efficiency solutions.
10 years of coding experience
10 years of employment as a software developer
Laurea Magistrale, Ingegneria Elettronica, Laurea Magistrale, Ingegneria Elettronica at Alma Mater Studiorum – Università di BolognaMaster of Science, Electrical Engineering, Master of Science, Electrical Engineering at Delft University of Technology
Italian, English, German
Github Skills (28)
systemverilog10
python10
risc-v10
bash10
script10
sys10
fpga10
embedded10
vivado10
tcl10
simulation9
xilinx9
simulations9
synthesis9
synthesize9
Programming languages (12)
Github contributions (5)
openhwgroup/cv32e40p
Feb 2016 - Feb 2020
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:21 commits, 1 PR, 1 tag in 4 years
Contributions summary:Francesco contributed significantly to the `riscv_tracer.sv` file, enhancing its functionality by adding print functions for various instruction types and debugging features. Their work also included the modification of `riscv_simchecker.sv` for simulation checking of the RISC-V core. Furthermore, the user adapted the build configuration, specifically deactivating tracing features for FPGA builds.
risc-vcpupulpuvmriscv
pulp-platform/common_cells
Sep 2015 - Jan 2018
Common SystemVerilog components
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:1 review, 18 commits, 2 PRs in 2 years 4 months
Contributions summary:Francesco primarily focused on modifying and adding SystemVerilog components related to clock gating, clock muxing, and clock buffering, particularly for Xilinx and TSMC055 architectures. The contributions involved adapting these components for FPGA emulation and implementing clock management features within the context of the PULP platform. The commits also included merging of branches, indicating integration efforts of the changes into the larger repository.
systemverilog
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