Summary
Gabriel Caffarena is an Open RAN Chip Development Manager and senior R&D leader with a 25-year academic and industry track record in ASIC/FPGA design, 5G baseband algorithms, and low-power VLSI. He leads multidisciplinary teams building ASIC/FPGA IP for MU‑MIMO and advanced baseband processing while holding six registered patents and drafting more on VLSI, Open RAN and AI. His research career spans top institutions (UCL, Imperial, Oxford, IMEC, INSA‑Rennes) with 90 publications and ~900 citations, reflecting strengths in fixed‑point/approximate computing, FPGA/GPU acceleration (CUDA, VHDL), and hardware acceleration for bioengineering applications. He has combined hands‑on chip development and university leadership—coordinating a Master in Biomedical Engineering and teaching across digital, analog and signal‑processing subjects—plus practical experience in chip verification (UVM). Based in Málaga, he brings a rare blend of academic rigour and product-focused IP delivery, and an unusual sideline in music and psychology that complements his interdisciplinary approach.
9 years of coding experience
13 years of employment as a software developer
MSc Telecommunications, MSc Telecommunications at Universidad de Málaga
PhD Training FPGA-based Signal Processing, PhD Training FPGA-based Signal Processing at Imperial College London
Bachelor's degree Psychology, Bachelor's degree Psychology at Universidad CEU San Pablo
Music, Music at Conservatorio Superior de Música de Málaga
Ph.D. Electronics, Ph.D. Electronics at Universidad Politécnica de Madrid
English, Spanish