Ganesh Gore
Principal Engineer at QuickLogic Corporation
Salt Lake City, Utah, United States
Summary
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Rockstar🎓
Top SchoolGanesh Gore is a Principal Engineer with 11 years of experience specializing in FPGA architecture, tooling, and tapeout workflows, currently leading customized FPGA design and signoff at QuickLogic Corporation. He combines hands-on hardware-software integration—having implemented HOSTMOT2 on Spartan6 and written Linux drivers for fast GPIO, UART and SPI—with backend and DevOps contributions to prominent open-source FPGA projects like OpenFPGA and VTR. His work improving CI build, memory reporting, and automated compilation scripts demonstrates a focus on scalable, maintainable toolchains that speed research-to-silicon cycles. Ganesh holds advanced degrees from IIT Bombay and is pursuing a PhD at the University of Utah, bringing academic rigor to commercial tapeout challenges. Based in Salt Lake City, he is equally comfortable in low-level driver development and high-level workflow automation—a blend that helps bridge lab prototypes to production silicon.
11 years of coding experience
11 years of employment as a software developer
Indian Institute of Technology BombayThe University of UtahBachelor of Engineering (BE) Electronics Engineering, Bachelor of Engineering (BE) Electronics Engineering at Vivekananda Institute of TechnologyDiploma Electronics & Telecommunication Engineering, Diploma Electronics & Telecommunication Engineering at L&T INSTITUTE OF TECHNOLOGY
Stackoverflow
113reputation
37kreached
1answer
5questions
Github Skills (20)
verilog10
python10
scripting10
cicd10
script10
fpga10
sh10
shell10
eda9
cad9
automation9
automations9
automated-tests8
url-routing8
multiprocessing6
Programming languages (8)
Github contributions (5)
lnis-uofu/OpenFPGA
Jun 2019 - Oct 2022
An Open-source FPGA IP Generator
Role in this project:
Backend Developer
Backend DeveloperContributions:48 reviews, 323 commits, 94 PRs in 3 years 5 months
Contributions summary:Ganesh appears to be focused on developing and maintaining aspects of the FPGA IP generator project. Their contributions involve adding architecture files and modifying scripts for automated compilation and testing. The user is making changes related to the compilation process by modifying run scripts.
fpga-socyosysedalatticefpga
verilog-to-routing/vtr-verilog-to-routing
Sep 2021 - Oct 2021
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:Backend & DevOps Engineer
Backend & DevOps EngineerContributions:4 reviews, 21 commits, 2 PRs in 1 month
Contributions summary:Ganesh primarily contributed to improving the build and memory logging within the continuous integration (CI) workflow. They also addressed code formatting and linting issues using automated tools. Furthermore, the user integrated memory usage reporting into the VPR run and implemented human-readable memory formatting. These changes demonstrate a focus on improving the efficiency and maintainability of the build process and associated tooling.
vtrcadedaplacementsynthesis
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