Gary Yeap is a Senior R&D Manager with 13+ years leading multinational teams to deliver commercial Physical Design CAD tools, currently driving placement and routing, flip-chip, 3DIC and packaging features in Synopsys' IC Compiler. He combines deep hands-on EDA expertise—from RTL-to-GDSII chip design through advanced 16/10nm foundry rules—with a research pedigree (Ph.D. in EE) and a rare background as both a chip designer and tool developer. Gary’s domain strengths include low-power architectures, floorplanning, and advanced packaging, and he has translated that knowledge into published work on Low Power Digital VLSI Design. Known for blending algorithmic innovation with practical product delivery, he excels at requirements, schedule and quality management across global teams and customer engagements. An engineer at heart, his GitHub aphorism ("寫不出 bug 就往 bug 裡寫") hints at a pragmatic, self-aware approach to problem solving and code craft.
13 years of coding experience
10 years of employment as a software developer
MS, EECS, MS, EECS at National Taiwan University
Ph.D., Electrical Engineering, Ph.D., Electrical Engineering at Northwestern University
Contributions:13 pushes, 1 branch in 4 years 9 months
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