Gaurav Patil
ASIC Design Engineer, Sr Staff Manager at Qualcomm
San Jose, California, United States
Summary
👤
Senior🎓
Top SchoolGaurav Patil is a senior ASIC design engineer and manager in San Jose with eight years of experience designing and delivering high-performance video codec and computer vision IPs. He leads micro-architecture, RTL development, and embedded software debugging for motion processing, feature descriptor cores, and semi-global matching blocks at Qualcomm. Comfortable in Verilog and C, he has driven timing, area, and power optimizations while owning both individual contributor and tech-lead responsibilities. Prior work includes pioneering Li-Fi PHY/MAC RTL and FPGA prototypes that cut transceiver latency dramatically and implemented adaptive data-rate and multi-transmitter schemes. He combines hands-on RTL/FPGA implementation with system-level testing and embedded software for pragmatic, production-ready IPs. Gaurav’s background—MS in Computer Engineering and end-to-end hardware/software debugging—means he often surfaces practical trade-offs others miss when tuning silicon blocks for real-world video and vision workloads.
8 years of coding experience
9 years of employment as a software developer
Master’s Degree Computer Engineering, Master’s Degree Computer Engineering at Arizona State UniversityBachelor’s Degree Electronics Engineering, Bachelor’s Degree Electronics Engineering at University of Mumbai
English, Hindi, Marathi
Github Skills (19)
localization6
strings6
android5
java5
uiimage5
ios4
nosql-database4
realm4
code-generator4
swift4
database4
uicolor3
react-native3
stencil2
sqlite2
Programming languages (3)
Github contributions (5)
pgaurav10/DBMS
Oct 2017 - Sep 2020
Contributions:2 pushes, 1 branch in 2 years 11 months
pgaurav10/DBMS_Project
Sep 2017 - Sep 2020
Contributions:7 pushes, 1 branch in 3 years
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