GeorgeĀ Chatzianastasiou
Electronics Engineer at CERN
Geneva Metropolitan Area Switzerland
Summary
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Top SchoolGeorge Chatzianastasiou is an electronics engineer with 9 years of hands-on experience in FPGA firmware, digital IC design and system-level verification, currently contributing to the ATLAS trigger upgrades at Brookhaven National Laboratory and CERN. He specializes in high-performance embedded systems, high-level synthesis, and UVM-based verification, having led verification teams for SoC/5G baseband FPGA solutions using cutting-edge Stratix 10 and Xilinx devices. His background blends academic rigor from Imperial College London with practical deployment on large-scale physics experiments, where he implements timing-constrained VHDL designs and hardware-in-the-loop validation. Comfortable moving between IP-level verification and system architecture, he brings a track record of coordinating cross-disciplinary teams to deliver complex, low-latency digital systems. An understated strength is his experience translating demanding experimental requirements into robust, testable FPGA firmware for mission-critical infrastructure.
9 years of coding experience
5 years of employment as a software developer
Master of Science (MSc), Analogue and Digital Integrated Circuit Design, Master of Science (MSc), Analogue and Digital Integrated Circuit Design at Imperial College LondonMaster of Engineering (MEng), Electrical, Electronics and Computer Engineering, 7.67/10, Master of Engineering (MEng), Electrical, Electronics and Computer Engineering, 7.67/10 at University of Thessaly
English, GreekGithub contributions (2)
constantinides/RAABB
Sep 2017 - Sep 2018
Contributions:6 commits, 1 push in 11 months
elchatzi19/hello-world
Oct 2016 - Oct 2016
Contributions:2 PRs, 3 pushes, 3 branches in 1 day
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