Georgiy Krylov
Assistant Professor at University of New Brunswick
Fredericton, New Brunswick, Canada
Summary
👤
Senior🎓
Top SchoolGeorgiy Krylov is an Assistant Professor and researcher with 11 years of experience at the intersection of high-performance computing, compiler/runtime design, FPGA CAD and emerging quantum computing. Based at the University of New Brunswick, he blends academia and industry collaboration, having supported IBM Toronto via a Mitacs internship and contributed significant backend improvements to the widely used open-source Verilog-to-Routing (VTR) FPGA toolchain. His work on ODIN_II introduced a novel optimization for mixing hard and soft logic to trade off frequency and device size, and he has focused on language-agnostic mechanisms to boost ahead-of-time compiler performance. An experienced instructor and curriculum developer, he has taught operating systems and concurrent programming across multiple institutions. He brings practical systems engineering skills—CUDA, FPGA synthesis, runtime environments—combined with rigorous PhD-level research, making him adept at turning theoretical ideas into reproducible tooling. Colleagues value him for shipping careful, test-hardened changes to complex open-source flows while maintaining a strong teaching portfolio.
11 years of coding experience
6 years of employment as a software developer
Doctor of Philosophy - PhD, Computer Science, Doctor of Philosophy - PhD, Computer Science at University of New BrunswickDiploma, University Teaching, Diploma, University Teaching at University of New Brunswick (Centre of Extended Teaching and Learning)Master's degree, Computer Science, Master's degree, Computer Science at Nazarbayev University
English, Russian, Kazakh
Github Skills (10)
fpga10
synthesis10
command-line-arguments10
verilog10
c-language10
cprogramming-language10
eda10
cad10
xml9
python8
Programming languages (3)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
Jul 2020 - Oct 2020
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:1 review, 11 commits, 5 PRs in 2 months
Contributions summary:Georgiy primarily contributed to the ODIN_II synthesis flow, focusing on optimizations and command-line argument enhancements. They introduced a new optimization strategy for mixing hard and soft logic implementations, enabling frequency and device size trade-offs. Their work included modifying the partial mapping stage and incorporating command-line arguments to control these optimizations. Furthermore, they addressed coverity scan errors and modified the VTR flow to accommodate custom ODIN II configurations through XML files, demonstrating a focus on improving and extending the tool's capabilities.
vtrcadedaplacementsynthesis
georgkrylov/local-vtr-verilog-to-routing
Nov 2019 - Aug 2021
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Contributions:134 pushes, 25 branches, 3 comments in 1 year 9 months
cadedasynthesisplacementrouting
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