Germain Haugou
Research Engineer at ETH Zurich
France
Summary
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RockstarGermain Haugou is a research engineer based in France with nine years of experience focused on embedded systems, verification, and low-level software for SoC platforms. He currently works at ETH Zurich and previously spent significant time as an embedded software engineer at GreenWaves Technologies and as an engineer at STMicroelectronics, giving him broad industry and research perspectives. His open-source contributions to the well-known PULPissimo project highlight practical expertise in testbench development and DPI-based integration of peripherals like UART, QSPI, CPI and JTAG, bridging hardware verification and software boot flows. Colleagues value his ability to navigate complex hardware architectures while improving verification methodology and debug infrastructure. He combines academic research rigor with hands-on engineering, often surfacing subtle testbench and boot-process fixes that improve system observability and reliability.
9 years of coding experience
16 years of employment as a software developer
Github Skills (13)
testbed10
verification10
testbench10
jtag10
formal-verification10
systemverilog10
hardware10
hardwareid10
sys9
embedded9
uart8
spi8
gpio7
Programming languages (10)
Github contributions (5)
pulp-platform/pulpissimo
Jun 2018 - Nov 2019
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:80 commits, 2 PRs, 68 pushes in 1 year 5 months
Contributions summary:Germain primarily contributed to the testbench environment for a PULPissimo platform, focusing on DPI (Direct Programming Interface) models to integrate external drivers and verification components. Their work involved modifying the testbench (`tb_pulp.sv`) to incorporate DPI models for peripherals like UART, QSPI, CPI, and GPIO, as well as JTAG and debug interfaces. The commits also included modifications to the JTAG test flow and boot process within the testbench, demonstrating an understanding of the hardware architecture and verification methodology.
pulpcpusocdomainelectrical-engineering
pulp-platform/pulp-sdk
Feb 2018 - Oct 2022
Contributions:2 releases, 1495 commits, 48 PRs in 4 years 8 months
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