Gregory Chadwick
Digital Hardware Lead Engineer at Fractile
Bristol, England, United Kingdom
Summary
🤩
Rockstar🎓
Top SchoolGregory Chadwick is a digital hardware leader with 11 years of experience designing and verifying CPU and system IP, now leading hardware at Fractile after heading hardware efforts at lowRISC. He combines deep academic foundations—a PhD in Computer Architecture from Cambridge—with hands-on industry experience at ARM, Broadcom and Intel, focusing on memory systems, prefetching and high-performance IC design. Gregory has been a key contributor to high-profile open-source silicon projects such as OpenTitan and the Ibex RISC-V core, driving interface reworks, PMP integration and test/coverage improvements. He blends RTL design, verification and test automation skills (notably enhancements to riscv-dv CSR and PMP handling) to improve robustness and integration of open CPU cores. Colleagues describe him as a pragmatic engineer who surfaces subtle system-level issues early, such as hart ID and core-sleep semantics, improving both documentation and testbenches alongside RTL.
11 years of coding experience
9 years of employment as a software developer
BA, Computer Science, First, BA, Computer Science, First at University of CambridgeDoctor of Philosophy (PhD), Computer Architecture, Doctor of Philosophy (PhD), Computer Architecture at Cambridge University
Github Skills (18)
hardware-designs10
verilog10
systemverilog10
python10
risc-v10
cpu-architecture10
verification10
microarchitecture10
sys10
embedded10
test-automation10
bit-manipulation9
debug9
digital-design9
hdl9
Programming languages (9)
Github contributions (5)
lowRISC/ibex
Sep 2019 - Nov 2022
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Role in this project:
Back-end Developer
Back-end DeveloperContributions:394 reviews, 301 commits, 431 PRs in 3 years 3 months
Contributions summary:Gregory's contributions primarily focused on modifying the Ibex RISC-V CPU core's interface, particularly addressing the addition of a hart ID and core sleep functionality. They made several code changes, including altering core interfaces to incorporate these new signals, modifying related files in both RTL and documentation, and updating the relevant testbench examples. The user addressed multiple bug fixes and implemented features, suggesting a focus on improving core functionality and its integration with the larger system.
risc-vcpuzeroibex32-bit
lowRISC/opentitan
Sep 2019 - Nov 2022
OpenTitan: Open source silicon root of trust
Role in this project:Back-end Developer
Back-end DeveloperContributions:861 reviews, 289 commits, 512 PRs in 3 years 3 months
Contributions summary:Gregory primarily focused on updating and integrating code from the upstream lowRISC/ibex repository into the lowrisc/opentitan project. Their contributions involved significant architectural changes, top-level interface modifications, and the addition of essential PMP modules. The work included adapting the codebase to the new Ibex top-level interface and integrating the RISC-V stream generator handshake. This user also added and fixed errors from a test file, and they also contributed to the design of test and coverage.
root-of-trustrootsilicontrust
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