Guanlin Zhang
Lead Analog Mixed-signal Design In 28Gbs SerDes For Intel A10 S10 FPGA, PLL CDR CTLE VGA at Oracle
California, United States
Summary
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Senior🎓
Top SchoolGuanlin Zhang is a lead analog/mixed-signal engineer based in California with over a decade of hands-on experience designing high-speed SerDes, PLLs, CDRs, CTLEs and VGAs for Intel A10/S10 FPGAs. He combines deep nanoscale CMOS analog expertise—mismatch, nonlinearity, offset cancellation, noise and signal/power integrity—with project leadership that aligns R&D scope to product marketing and system architecture. At Intel (and previously Oracle) he has driven link-budget optimization and post-silicon validation, reducing iteration overhead while achieving first-silicon functionality on mission-critical designs. Known for strong cross-functional collaboration, superior troubleshooting, and a business-oriented mindset, he also pursues low-power, high-speed connectivity applications from IoT to autonomous systems. An unusual strength is his physics-rooted approach to circuit/model correlation, which helps bridge theoretical limits and practical silicon implementation.
8 years of coding experience
Physics & Electrical Engineering, Physics & Electrical Engineering at Nanjing UniversityElectrical & Computer Engineering, Electrical & Computer Engineering at University of California, IrvineProgramming languages (1)
Github contributions (5)
largerthanlife/100-C-Problems
Mar 2018 - Apr 2018
Contributions:53 commits, 47 pushes, 1 branch in 1 month
largerthanlife/Project-of-POP
Apr 2018 - Jun 2020
Contributions:6 pushes, 1 branch in 2 years 2 months
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