Guillaume Chauvon
Digital Designer at Thales Digital Identity and Security (ex Gemalto)
Aix-en-Provence, Provence-Alpes-Côte d'Azur, France
Summary
🤩
Rockstar🎓
Top SchoolGuillaume Chauvon is a digital designer and engineer with four years’ experience building and automating complex verification and CI/CD infrastructures for RISC-V cores at Thales Digital Identity and Security. He combines hands-on back-end and DevOps skills—having improved simulators, test suites and release pipelines for notable open-source projects like CORE-V CVA6—with hardware-oriented design work such as implementing a coprocessor interface and contributing to the CoreV-eXtension specification. Comfortable in cross-disciplinary teams, he brings embedded Linux and energy-aware system design experience from academic projects and internships. Based in Aix-en-Provence, he prefers collaborative problem solving and is skilled at turning specification-level ideas into reliable, testable implementations.
4 years of coding experience
Diplôme d'ingénieur, Ingénierie microélectronique et informatique, Diplôme d'ingénieur, Ingénierie microélectronique et informatique at École des Mines de Saint-ÉtiennePHYSICAL SCIENCES, PHYSICAL SCIENCES at Lycée Blaise Pascal Rouen
Github Skills (18)
systemverilog10
python10
scripting10
risc-v10
verification10
cicd10
automation10
script10
systemverilog-hdl10
ci-cd-pipeline10
sh10
automations10
shell10
uvm9
cpu9
Programming languages (3)
Github contributions (5)
openhwgroup/cva6
Nov 2021 - Dec 2022
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Back-end Developer & DevOps Engineer
Back-end Developer & DevOps EngineerContributions:22 reviews, 20 commits, 58 PRs in 1 year
Contributions summary:Guillaume significantly contributed to the CVA6 project by addressing code-related issues and enhancing the project's build and test infrastructure. They modified and improved the simulator configuration, specifically addressing the interaction with various ISS and simulation tools. The user also added support for new features like the CV-X-Interface, which involved core modifications and coprocessor integration. Furthermore, they modified the testing scripts and test configurations to improve the testing of the CVA6 processor.
cpurisc-vasicbootingariane
openhwgroup/core-v-verif
Nov 2021 - Oct 2022
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:Automation Engineer / Build & Release Engineer
Automation Engineer / Build & Release EngineerContributions:6 reviews, 35 commits, 24 PRs in 11 months
Contributions summary:Guillaume primarily focused on enhancing the Continuous Integration and Continuous Delivery (CI/CD) pipeline and test infrastructure for the project. Their contributions include adding scripts for running tests with different simulators, creating a custom test template, and integrating benchmark jobs. The user also made modifications to the test configuration, including updating simulators, to ensure accurate and efficient testing. Additionally, the user addressed minor code issues and improved reporting capabilities.
risc-vsystemverilogriscverificationcores
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