Hanqing Zeng
Research Scientist at Meta
Menlo Park, California, United States
Summary
🤩
Rockstar🎓
Top SchoolHanqing Zeng is a Research Scientist at Meta AI with a PhD in Computer Engineering from USC and 11 years of experience tackling memory- and compute-intensive problems. His work advances scalable graph representation learning—developing minibatch sampling algorithms and subgraph-based GNN designs that improve accuracy and training efficiency on production-scale graphs. He pairs algorithmic innovations with architecture-aware acceleration across GPUs, CPUs and FPGAs, including contributions to an open-source FPGA CAD flow (vtr-verilog-to-routing) to speed up core analysis tools. Known for decoupling GNN depth from receptive field and for practical engineering that moves research into infrastructure, he blends rigorous theory with production-focused systems design. Based in Menlo Park, he brings uncommon depth in co-optimizing algorithms and heterogeneous hardware for large-scale ML.
11 years of coding experience
7 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Computer Engineering, Doctor of Philosophy (Ph.D.), Computer Engineering at University of Southern CaliforniaUndergraduate Exchange, Electrical and Computer Engineering, Undergraduate Exchange, Electrical and Computer Engineering at University of TorontoThe University of Hong Kong (HKU)
Chinese, English
Github Skills (9)
c1710
fpga10
verilog10
c1110
eda10
performance-optimization9
url-routing9
cad8
python8
Programming languages (2)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
May 2015 - Aug 2015
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:31 commits, 19 pushes, 1 branch in 3 months
Contributions summary:Hanqing's commits primarily focus on enhancing the benchtracker plotter, a tool likely used for analyzing and visualizing data related to FPGA research. Their contributions include improving the plotter's functionality by adding features like data exporting and fixing bugs. Furthermore, the user added code to print out the switch usage status, which is a core feature for FPGA design and analysis, and significantly improved the speed of this feature. The user also fixed a bug in the architecture files related to the switch blocks.
vtrcadedaplacementsynthesis
ZimpleX/neural-net-bp
Oct 2015 - Jul 2016
Contributions:175 pushes, 4 branches in 9 months
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