Summary
Hanran Wu is a GPU-focused computer architect and systems engineer with six years of hands-on experience spanning GPU architecture, embedded robotics, and supply-chain software. Currently pursuing an MS in Computer Science at Georgia Tech, Hanran developed virtual memory for a RISC-V-based GPU in C++ and SystemVerilog and benchmarked OpenCL workloads on cycle-level and FPGA simulations. Past internships at NVIDIA and Samsung Semiconductor complement research on RL-driven legged locomotion (ICRA 2024) and energy-aware GNN quantization that cut inference energy by 30% with minimal accuracy loss. Equally comfortable in low-level RTL and high-level system design, Hanran has shipped practical tooling—such as a Python MVC GUI and Dockerized CI/CD pipelines—that boosted manufacturing efficiency and developer productivity. Known for bridging academia and industry, he combines FPGA deployments, compiler exploration (LLVM/RISC-V GCC), and open-source robot control code to accelerate prototyping and reproducible research. Always eager for hard problems, he focuses on large-scale and edge intelligence with a curiosity for physical simulation and memory-system tradeoffs.
6 years of coding experience
3 years of employment as a software developer
Master of Science - MS, Computer Science, Master of Science - MS, Computer Science at Georgia Institute of Technology
High School Diploma, High School Diploma at Guangzhou Foreign Language School
English, Chinese, Chinese, French