Haoyuan Feng
Analyst at VM Wealth Management
Singapore
Summary
🤩
Rockstar🎓
Top SchoolHaoyuan Feng is an analyst with four years of experience blending rigorous academic training in accounting, econometrics and valuation from Columbia Business School and NYU with practical investment and wealth-management roles across Singapore and China. He has worked on due diligence and financial modeling at CDF Ventures and Minsheng Securities, and now advises client portfolios and product selection at VM Wealth Management. Beyond finance, Haoyuan contributes to high-performance open-source systems—helping architect and debug a RISC-V processor project—demonstrating rare cross-disciplinary fluency in Python, Java, R and low-level system work. This combination of PhD-level quantitative coursework, hands-on investment experience, and systems engineering work gives him a distinctive edge in analyzing complex financial and technical problems.
4 years of coding experience
Master of Science - MS, Accounting and Fundamental Analysis, Master of Science - MS, Accounting and Fundamental Analysis at Columbia Business SchoolBachelor of Arts - BA, Economic, Mathematics, 3.6, Bachelor of Arts - BA, Economic, Mathematics, 3.6 at New York University
Github Skills (9)
hdl10
risc-v10
mmu10
microarchitecture10
chisel10
systemverilog9
performance-optimization9
debug9
debugging9
Programming languages (7)
Github contributions (5)
OpenXiangShan/XiangShan
Oct 2022 - Jan 2023
Open-source high-performance RISC-V processor
Role in this project:
Back-end Developer & System Architect
Back-end Developer & System ArchitectContributions:172 reviews, 15 commits, 174 PRs in 3 months
Contributions summary:Haoyuan contributed to the development and debugging of the XiangShan RISC-V processor. Their work included adding support for FST waveform dumping, fixing bugs related to signal width specification in the ROB and MMU, and increasing MMU timeout values. Furthermore, the user implemented ChiselDB and Fake PTW modules, improving MMU functionality and adding difftest checks for L1 and L2 TLBs. These contributions suggest involvement in system architecture and performance optimization.
risc-vcpuriscvperformancemicroarchitecture
good-circle/XiangShan
Jan 2023 - Jul 2023
Open-source high-performance RISC-V processor
Contributions:14 pushes, 258 branches in 6 months
risc-vcpuriscvriscv32performance
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