Haroon Shafique is a Senior CPU Verification Engineer with six years of hands-on experience designing and verifying high-performance Arm and RISC-V processors, currently focused on Cortex CPU memory subsystem verification at Arm. He combines deep SystemVerilog/UVM expertise with low-level C and Assembly test development, Python-based automation (CocoTB), and build tooling to drive coverage-closed DV flows and root-cause RTL debug. Haroon has led verification efforts for server-grade RISC-V cores, developed architecture-level test plans and UVM environments, and mentored junior engineers while owning end-to-end verification delivery and client-facing technical communication. His background in research (EE/Computer Engineering), EEG-based ML work, and several years teaching math and physics give him a rare blend of pedagogical clarity and system-level reasoning. He also initiated and led an open-source RISC-V DV project integrating riscv-dv and Spike, demonstrating both community engagement and practical tooling expertise.
6 years of coding experience
4 years of employment as a software developer
High School Pre-engineering, High School Pre-engineering at Government College University, Lahore
Bachelor's degree Electrical Engineering (Specialization Computer Engineering), Bachelor's degree Electrical Engineering (Specialization Computer Engineering) at University of Engineering and Technology, Lahore
Contributions:5 commits, 4 pushes, 1 branch in 1 day
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Haroon Shafique - Senior Engineer - CPU Verification