Harrison Liew
Senior Research Scientist at Intel Corporation
Portland, Oregon, United States
Summary
🤩
Rockstar🎓
Top SchoolHarrison Liew is a Senior Research Scientist at Intel with 11 years of experience in VLSI, IC and circuit design, and systems-level hardware research, currently based in Portland, Oregon. He brings deep academic rigor from a PhD program at UC Berkeley and practical industry chops from roles at Intel, Analog Bits, Boeing, and other aerospace and defense firms. Harrison has contributed to prominent open-source hardware tooling—working on Chipyard's physical design and VLSI flow and integrating the ASAP7 PDK—demonstrating strength in bridging research, layout/GDS workflows, and power/simulation infrastructure. He excels at taking complex SoC examples to tapeout-ready flows and has a track record of accelerating prototype development across heterogeneous platforms. Colleagues rely on him for pragmatic solutions that reduce simulation and power-estimation friction while preserving research-grade innovation.
11 years of coding experience
3 years of employment as a software developer
Doctor of Philosophy - PhD, Electrical Engineering, Doctor of Philosophy - PhD, Electrical Engineering at University of California, BerkeleyWest Windsor-Plainsboro High School SouthMaster of Science (MS), Electrical Engineering, Master of Science (MS), Electrical Engineering at Columbia Engineering
Chinese, Chinese, French
Github Skills (6)
simulations10
simulation10
vlsi10
dvcs9
verilog8
rt8
Programming languages (8)
Github contributions (5)
ucb-bar/chipyard
Aug 2019 - Oct 2022
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Role in this project:
Hardware Engineer
Hardware EngineerContributions:98 reviews, 59 commits, 40 PRs in 3 years 2 months
Contributions summary:Harrison's contributions primarily focused on the physical design and VLSI flow for a RISC-V SoC. They made modifications to the example design, and added a view_gds.py script for viewing the layout. Also, they addressed issues relating to simulation and power estimation by modifying the sim and power make targets. Their work involves integration of the ASAP7 PDK.
rtlout-of-orderhardware-designsvlsicomputer-engineering
harrisonliew/cs252_ee290_project
Mar 2020 - May 2020
CS252 & EE290 Project, Spring 2020
Contributions:23 pushes, 139 branches, 4 tags in 1 month
spring-bootspringjavaspring-security
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