Harry Callahan
Senior HW SW Engineer at lowRISC CIC
Cambridge, England, United Kingdom
Summary
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Rockstar🎓
Top SchoolHarry Callahan is a Senior HW/SW Engineer based in Cambridge with four years of professional experience focused on embedded systems, verification, and automation for open-source silicon projects. At lowRISC he drives both hardware and software integration—contributing SystemVerilog test environments for OpenTitan’s SPI host and streamlining CI, simulation, and verification flows for the Ibex RISC‑V core. His background includes hardware and electronic design roles at Blackmagic and Renishaw, giving him hands‑on product engineering experience from prototype to production. Comfortable across test automation, firmware C code, and build/devops improvements, he blends low‑level hardware insight with pragmatic tooling to keep complex simulations running reliably. An Oxford‑trained engineer, he brings a habit of refining verification infrastructure that often yields outsized productivity gains behind the scenes.
4 years of coding experience
6 years of employment as a software developer
MEng in Engineering Science Keble College, MEng in Engineering Science Keble College at University of Oxford
Github Skills (24)
systemverilog10
python10
uvm10
risc-v10
git-repository10
verification10
hardware10
formal-verification10
sys10
embedded10
github-repos10
hardwareid10
test-automation10
cicd9
c119
Programming languages (6)
Github contributions (5)
lowRISC/ibex
Mar 2022 - Nov 2022
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Role in this project:
Full-stack Developer & DevOps Engineer
Full-stack Developer & DevOps EngineerContributions:110 reviews, 77 commits, 84 PRs in 7 months
Contributions summary:Harry made contributions focused on improving the build, testing, and simulation processes for the Ibex RISC-V CPU core. Their work included refactoring scripts to enable parallelism within the verification flow, and implementing features such as a wall-clock timeout mechanism to ensure simulations complete gracefully. They also updated the codebase to use a new coverage merging tool and addressed code issues. These changes streamlined the continuous integration and testing.
risc-vcpuzeroibex32-bit
lowRISC/opentitan
Nov 2022 - Nov 2022
OpenTitan: Open source silicon root of trust
Role in this project:Embedded Systems Engineer / Test Automation Engineer
Embedded Systems Engineer / Test Automation EngineerContributions:554 reviews, 5 commits, 146 PRs in 13 days
Contributions summary:Harry primarily focuses on developing and testing aspects of the OpenTitan project, specifically related to the SPI host interface. Their commits demonstrate expertise in SystemVerilog, with modifications to test sequences and environments. The user contributes to creating and refining tests to ensure the reliability and functionality of the SPI host within the OpenTitan hardware design. They also make changes to the C code used in the software tests.
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