Summary
Harsha Thyagaraja is a Member of Technical Staff with 10 years of experience in memory subsystem validation and high-performance computing hardware debugging, currently leading DDR5 memory debug and execution for Intel's Aurora supercomputer project and now contributing at Pure Storage. He brings deep systems-level expertise from roles at Intel, IBM, and Mphasis, combining test-engineering rigor with hands-on delivery of complex hardware-software integration. Based in Bengaluru, he specializes in root-cause analysis and validation strategies for cutting-edge memory subsystems, translating low-level signal and timing issues into actionable fixes. Known for bridging cross-functional teams under tight deadlines, he pairs strong technical ownership with practical execution on large-scale compute platforms.
10 years of coding experience
13 years of employment as a software developer
Bachelor of Engineering (BE), Computer Science, Bachelor of Engineering (BE), Computer Science at Atria Institute Of Technology
Pre University, PCMB, Pre University, PCMB at Sri Bhagawan Mahaveer Jain College
Carmel high School
English, Kannada, Hindi, Tamil