Summary
Hatim Kanchwala is an RTL Design Engineer with 11 years of experience, currently designing and optimizing micro-architecture for the Geometry Processing Cluster of Adreno GPUs at Qualcomm. He brings deep RTL expertise in SystemVerilog, timing closure and high-frequency GPU design, and a track record of high-quality micro-architecture documentation praised by peers. His background blends academic rigor from an M.Sc. at RWTH Aachen with hands-on FPGA and HLS systems work—integrating Xilinx boards into co-simulation platforms and automating bitstream toolchains for real-time simulators. Earlier projects include building a Verilog model of the historic EDSAC on open-source toolchains and advanced tracking-filter research for DRDO, reflecting a habit of tackling both legacy reconstruction and cutting-edge control problems. Based in Bengaluru, he thrives at the intersection of hardware design, automation, and performance engineering, often delivering pragmatic automation that speeds prototyping and verification.
11 years of coding experience
4 years of employment as a software developer
Bachelor of Technology - B.Tech., Bachelor of Technology - B.Tech. at Indian Institute of Technology, Patna
Master of Science - M.Sc., Master of Science - M.Sc. at RWTH Aachen University
Class XII Maharashtra Higher Secondary Certificate, Class XII Maharashtra Higher Secondary Certificate at Deogiri College Aurangabad
Class X Central Board of Secondary Education, Class X Central Board of Secondary Education at Nath Valley School
Hindi, English, German