Heera Nand is a Senior Engineering Manager with 12 years of experience leading high-performance computing and machine learning teams, currently overseeing ML solutions and Vitis applications at AMD. He has a strong FPGA and tooling background from a long tenure at Xilinx, where he advanced SDAccel/SDSoC and Vivado flows and managed application engineering teams for FPGA-based HPC. Skilled in Python, C/C++, Tcl, Perl and SystemC, he combines hands-on kernel and backend development—contributing RTL and OpenCL C++ examples to the well-known Xilinx/SDAccel_Examples repo—with strategic product leadership. Heera’s career began in SystemC/HLS-driven SoC and cryptography IP development at NEC, giving him uncommon depth in hardware-software co-design and verification. Known for improving hardware emulation and performance benchmarking, he blends low-level optimization expertise with people leadership to drive production ML systems on accelerator platforms.
12 years of coding experience
11 years of employment as a software developer
BE, Electronics & Communcation Engineering, BE, Electronics & Communcation Engineering at M.B.M. Engineering College, Jodhpur
Contributions:290 commits, 3 PRs, 17 pushes in 3 years 8 months
Contributions summary:Heera added multiple examples using RTL kernels. These examples include RTL adders with pipes, vector addition, and an IDCT kernel. They made edits to existing examples, including the addition of examples using OpenCL C++ API calls. The user also updated Makefiles and Readme documentation.
Contributions:12 commits, 14 PRs, 20 pushes in 3 years 1 month
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