Heinz Riener
R&D Engineer at Cadence Design Systems
Feldkirchen, Bavaria, Germany
Summary
👤
Senior🎓
Top SchoolHeinz Riener is an R&D engineer with 11 years of experience specializing in logic synthesis and formal methods for CAD and verification of hardware and software systems. After earning a Ph.D. in Computer Science, he advanced academic research as a postdoc at EPFL—where his logic synthesis libraries were recognized as an open science champion—and now applies that expertise at Cadence Design Systems. He is an active contributor to foundational open-source projects in the field, including core work on the widely used Berkeley ABC system and algorithmic enhancements to the mockturtle C++ logic network library. His work blends low-level back-end development, algorithm design for reconvergence-driven cuts, and a strong emphasis on code quality and verifiable correctness. Based in Bavaria, he brings a pragmatic researcher’s rigor to industrial R&D, often turning theoretical methods into production-ready tools.
11 years of coding experience
10 years of employment as a software developer
Doctor of Engineering (Ph.D.), Computer Science, Computer Science, Doctor of Engineering (Ph.D.), Computer Science, Computer Science at University of BremenMaster's Degree (Dipl.-Ing.), Telematik, Telematik, Master's Degree (Dipl.-Ing.), Telematik, Telematik at Technische Universität Graz
German, English, French
Github Skills (10)
c1710
data-structures10
algorithms10
c-language10
formal-verification10
c1110
cprogramming-language10
data-structure10
testing9
computer-engineering8
Programming languages (9)
Github contributions (5)
lsils/mockturtle
May 2018 - Mar 2022
C++ logic network library
Role in this project:
Back-end Developer
Back-end DeveloperContributions:1 release, 280 commits, 318 PRs in 3 years 10 months
Contributions summary:Heinz primarily focused on implementing reconvergence-driven cut algorithms and integrating them into the C++ logic network library, mockturtle. The commits include adding the `reconv_cut` algorithm with multiple pivots, improvements to the underlying data structures, and improvements to the fanout API for this purpose. This work also involved modifying existing code, adding test cases, and updating documentation to reflect the new functionality and enhancements.
logiccppc-plus-plus
berkeley-abc/abc
Mar 2017 - Jan 2019
ABC: System for Sequential Logic Synthesis and Formal Verification
Role in this project:Back-end Developer
Back-end DeveloperContributions:8 commits, 6 PRs, 3 comments in 1 year 10 months
Contributions summary:Heinz primarily contributed to the core logic and functionality of the ABC system. Their commits involve modifications to header files, and source code, implementing features related to sequential logic synthesis, formal verification, and ESOP-PLA file integration. They also addressed issues related to data types and compilation, reflecting a focus on code quality and correctness within the project's domain.
edasynthesisformal-verificationformalabc
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