Hemanth S
Design And Verification
Bengaluru, Karnataka, India
Summary
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Senior🎓
Top SchoolHemanth S is a Design and Verification engineer with 11 years of experience focused on RTL design, SystemVerilog-based functional verification, and ASIC/SoC methodologies, currently working at Maven Silicon from Bengaluru. Trained in Electronics and Communication Engineering (BE, CGPA 8.54), he combines hands-on RTL/Verilog coding with assertions-driven verification and a practical grasp of C and Python for automation. He is deepening physical design skills through a government-supported PMKVY IC design program that spans RTL-to-physical flows, signaling a commitment to full-chip development. Known for blending project leadership with technical execution, he brings an engineer’s attention to correctness and efficiency to semiconductor design challenges.
11 years of coding experience
Higher Secondary, 85.54%, Higher Secondary, 85.54% at St. Joseph's College higher secondary school TiruchirappalliBachelor of Engineering - BE, Electronics and Communications Engineering, CGPA: 8.54, Bachelor of Engineering - BE, Electronics and Communications Engineering, CGPA: 8.54 at K.Ramakrishnan College of Engineering
English, Tamil, TeluguGithub contributions (5)
hemus2121/DSA
Aug 2021 - Dec 2022
Contributions:163 commits, 309 pushes in 1 year 4 months
hemus2121/Leetcode-GFG
Jul 2022 - Mar 2023
Contributions:655 pushes in 8 months
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