Henrik Green
Software Engineering Manager For Security at Silicon Labs
Oslo, Norway
Summary
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RockstarHenrik Green is a Software Engineering Manager for Security at Silicon Labs in Oslo with about five years of engineering and verification experience. He blends leadership with hands-on verification expertise, having contributed significantly to open-source RISC-V verification projects like CORE-V and riscv-dv. His work focused on test automation, enhancing verification environments, and extending support for bit-manipulation extensions, improving coverage and robustness of processor verification. Henrik’s background bridges embedded systems and security engineering, ensuring secure, well-verified silicon and firmware. Notably, he brings practical experience tuning instruction generators and simulation tooling—skills that help translate low-level design changes into reliable verification outcomes.
5 years of coding experience
Github Skills (21)
systemverilog10
computer-architecture10
architecture10
uvm10
risc-v10
verification10
makefile10
sys10
instruction-set10
embedded10
architectures10
test-automation10
bit-manipulation9
cpu9
systemverilog-hdl9
Programming languages (7)
Github contributions (5)
openhwgroup/core-v-verif
Mar 2021 - Jan 2023
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:
Test Automation Engineer
Test Automation EngineerContributions:643 reviews, 268 commits, 410 PRs in 1 year 11 months
Contributions summary:Henrik primarily contributed to the functional verification project for the CORE-V family of RISC-V cores. Their commits focused on enhancing the verification environment by adding new test targets, modifying existing test structures, and integrating configuration options. These changes included updates to the build system, simulation scripts, and test programs, improving the robustness and coverage of the verification process. The user also fixed several error messages and updated code to support bitmanip extension tests.
risc-vsystemverilogriscverificationcores
chipsalliance/riscv-dv
Jul 2021 - Jul 2022
Random instruction generator for RISC-V processor verification
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:2 reviews, 5 commits, 5 PRs in 1 year
Contributions summary:Henrik primarily contributed to the verification of a RISC-V processor. Their work involved modifying instruction definitions and coverage models to support the bit manipulation extensions. They fixed issues related to immediate lengths, and also added register definitions for privilege and debug specifications. The user also addressed an issue with the C_JALR instruction.
risc-vriscinstructionverification
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