Henry Cook
Senior Principal Engineer at SiFive
Berkeley, California, United States
Summary
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Top School
Top expert inDigital Hardware Design and Verification
Henry Cook is a Senior Principal Engineer with 15 years of experience designing and optimizing RISC-V processors and hardware design tooling, currently leading architecture and implementation efforts at SiFive in Berkeley. He brings deep expertise in microarchitecture, cache and branch-prediction design, and parallel software for multicore systems—work grounded in a PhD from UC Berkeley where he co-developed Chisel generators for RISC-V under Patterson and Asanović. His open-source contributions include performance-focused multithreading tests and matmul optimizations for RISC-V, substantive ICache/BTB improvements to the BOOM core, and core enhancements to the Chisel hardware language. Known for bridging research and production silicon, he combines compiler- and backend-level fluency with pragmatic engineering that improves both verification and runtime efficiency.
15 years of coding experience
17 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Computer Science, Doctor of Philosophy (Ph.D.), Computer Science at University of California, BerkeleyB.S., Computer Science, B.S., Computer Science at University of Virginia
Github Skills (24)
multithreading10
matrix-multiplication10
risc-v10
c1110
c1710
scala10
chisel10
rt10
firrtl9
sys9
embedded9
assembler8
compiler-construction8
parallel-computing8
assembly8
Programming languages (7)
Github contributions (5)
riscv-software-src/riscv-tests
Jun 2013 - Dec 2014
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:8 commits in 1 year 6 months
Contributions summary:Henry primarily focused on developing and updating multithreading tests for the RISC-V software. They implemented and modified matrix multiplication (matmul) algorithms optimized for multi-core environments, including different versions for performance comparison. Code changes include modifications to data structures, barrier synchronization, and loop structures to improve thread utilization.
chipsalliance/chisel
Aug 2015 - Jul 2019
Chisel: A Modern Hardware Design Language
Role in this project:Backend Developer & Compiler Engineer
Backend Developer & Compiler EngineerContributions:20 reviews, 59 commits, 2 PRs in 4 years
Contributions summary:Henry made several contributions focused on improving the Chisel hardware design language. This involved refining the core Chisel library, including modifying permissions, updating test cases for compilation, and enhancing type safety within switch and is blocks. The user also worked on removing backend references, streamlining the driver, and improving macro hygiene.
rtlasicvhdllanguage-designeda
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