Hideto Ueno
Staff Engineer at SiFive
Milpitas, California, United States
Summary
🤩
Rockstar🎓
Top SchoolHideto Ueno is a Staff Engineer with nine years of experience specializing in compiler backends and hardware design tooling, currently advancing CIRCT at SiFive’s Platform Engineering team. He has a strong track record contributing to high-profile open-source projects such as LLVM/CIRCT and Chisel, improving FIRRTL-to-HW codegen, verification intrinsics, and toolchain integration for better Verilog output. Trained at the University of Tokyo (BSc/MSc in Computer Science), he blends research-grade rigor with practical engineering from multiple industry internships including Amazon and Preferred Networks. Notably, his contributions reveal a focus on preserving aggregates and adding hardware assertion/DPI intrinsics—small but impactful changes that improve verification and downstream synthesis quality.
9 years of coding experience
3 years of employment as a software developer
University of Tokyo
Github Skills (12)
verilog10
cil10
firrtl10
systemverilog10
cct10
chisel10
scala9
back-end-development9
code-generation9
dpi7
rt6
chip86
Programming languages (11)
Github contributions (5)
llvm/circt
Oct 2020 - Jan 2023
Circuit IR Compilers and Tools
Role in this project:
Back-end Developer
Back-end DeveloperContributions:22 releases, 1562 reviews, 545 commits in 2 years 3 months
Contributions summary:Hideto primarily worked on adding and improving features for the FIRRTL (Flexible Intermediate Representation for RTL) and SV (System Verilog) dialects within the CIRCT (Circuit IR Compilers and Tools) project. Their contributions focused on enhancing the code generation capabilities for the FIRRTL to HW backend and included implementing new operators, such as `dshlw`, adding verification for existing operators (bits, instance), and refining the merging of connections to optimize generated code. They also made improvements to the project's name handling and organization.
compilersbazelmlircircuitunikernel
chipsalliance/chisel
Apr 2022 - Apr 2022
Chisel: A Modern Hardware Design Language
Role in this project:Backend Developer & Verification Engineer
Backend Developer & Verification EngineerContributions:25 reviews, 1 commit, 8 PRs in 1 day
Contributions summary:Hideto contributed to the Chisel project, a hardware design language, focusing on changes related to the CIRCT (MLIR FIRRTL Compiler) integration. Their work involved modifying the `ChiselStage` and related files to support features like aggregate preservation, and introducing intrinsics for hardware assertions and DPI (Direct Programming Interface) calls. These changes suggest a focus on improving the toolchain and verification capabilities of the Chisel language.
rtlasicvhdllanguage-designeda
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