Hodjat Esfeden
Senior Silicon Engineer at Google
Sunnyvale, California, United States
Summary
🤩
Rockstar🎓
Top SchoolHodjat Esfeden is a Senior Silicon Engineer at Google with a Ph.D. in Computer Science from UC Riverside and over five years of hands-on experience in silicon design verification, tools/flows/methodologies, and GPU compiler and architecture solutions. His research-driven background focuses on maximizing GPU utilization for machine learning workloads and adding architectural support for security, bridging academic rigor with production hardware engineering. At Google he progressed from intern and student researcher roles to senior engineer, contributing to verification toolchains and test automation—most notably integrating PyVSC into the widely used chipsalliance/riscv-dv random instruction generator to enhance functional coverage. Based in Sunnyvale, he combines deep computer-architecture expertise with practical automation skills, and maintains a personal site showcasing his work and publications.
5 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy (Ph.D.) Computer Science, Doctor of Philosophy (Ph.D.) Computer Science at University of California, RiversideBachelor's degree Computer Engineering, Bachelor's degree Computer Engineering at Sharif University of Technology
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (4)
constraint-programming10
python10
test-automation10
risc-v9
Programming languages (2)
Github contributions (5)
chipsalliance/riscv-dv
Jun 2020 - Jul 2022
Random instruction generator for RISC-V processor verification
Role in this project:
Backend Developer & Test Automation Engineer
Backend Developer & Test Automation EngineerContributions:133 reviews, 81 commits, 60 PRs in 2 years
Contributions summary:Hodjat primarily contributed to the project by importing and integrating the PyVSC module, a constraint programming and coverage collection library, into the RISC-V instruction generator. This integration involved modifications to several Python files, including `riscv_instr.py`, `riscv_instr_gen_config.py`, and `riscv_instr_pkg.py`, to support functional coverage testing. The user also extended the `riscv_instr_cov_test.py` file, adding methods and pre-sampling extensions. These changes suggest an effort to enhance the testing capabilities of the RISC-V instruction generator.
risc-vriscinstructionverification
hodjat91/riscv-dv
Jun 2020 - Jul 2020
SV/UVM based instruction generator for RISC-V processor verification
Contributions:5 pushes in 24 days
risc-vcpudubpongrisc
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